1. Field of the Invention
The present invention relates to methods of manufacturing arrays of memory cells, and more specifically, to a method of optimizing the cost of manufacturing such devices by considering both the cost of manufacturing different capacity memory chips and of assembling multiple memory chips into larger capacity memory array packages. The inventive method can also be applied to optimize the manufacture of an array of logic gates or similar devices.
2. Description of the Prior Art
Memory is an essential component of computers as well as many other types of electronic devices. As the functionality of these devices increase, so does the demand for additional memory capacity. Thus, it becomes important to determine the most economically efficient way to provide the desired memory capacity. However, there are many factors which influence the cost of a specified size memory array. These include the cost of the semiconductor material (wafer) from which the individual memory chips (die) are fabricated, the cost of processing the wafer to form the desired memory elements, the cost of manufacturing chip carriers or substrates to hold multiple chips, the cost of assembling multiple chips onto a carrier, the cost of mounting multiple chip carriers to a substrate and packaging the substrate, and the cost of testing the packaged devices.
The cost of the semiconductor material (e.g., silicon) used to fabricate an integrated circuit chip having a large number of memory cells or logic gates is a function of the yield (Y) of the fabrication process flow used to form the chip (or die) from the wafer. The yield is a function of both the area (A) of the die on which the memory cells are formed and the density of the defects generated during the fabrication process (expressed in terms of defects per unit area). A yield function dependent on the die area and defect density can be used to determine the percentage of usable die yielded by the process flow. This factor can then be multiplied by the number of die fabricated to determine the number of usable die produced by the process flow from a given size wafer. Most yield functions for commonly used fabrication processes are non-linear with respect to die size, i.e., the percentage of usable yielded dies decreases at a faster rate than the die size increases. Assuming a fixed size for a single memory cell, this means that the cost of manufacturing an array of memory cells increases at a faster rate than that at which the number of memory cells on a die increases. Thus, the fabrication cost per memory cell is an increasing function of the memory die size.
The non-linear increase of the semiconductor material and fabrication cost as a function of the memory cell or logic gate capacity of a die means that the cost of fabricating a large capacity memory chip can quickly become prohibitive for some applications. Yet, these same applications may require a large amount of available memory or large number of logic gates to provide a desired range of functions.
Traditionally, the demand for increased memory capacity has been addressed by developing larger capacity memory chips, i.e., single chips having a greater number of memory cells. This has been the motivation behind the enormous development costs and time directed to the design and fabrication of memory chips having a capacity of 8 k (8 thousand), 16 k, 32 k, 64 k, etc. memory cells. However, with the size of a memory cell remaining approximately constant, this means that the size of the chip increases approximately linearly as the capacity increases. With the manufacturing costs for a single high capacity memory chip increasing faster than the number of memory cells on the chip, the cost per bit of memory increases as the capacity of the chip increases. Thus, satisfying the need for higher capacity memory or logic gate arrays by manufacturing larger capacity memory or logic gate chips may not be the most economically efficient response to the problem.
What is desired is a method of optimizing the cost of manufacturing high capacity memory or logic gate arrays. The method should enable a designer to determine how to provide the amount of memory or logic gates needed for an application in the most cost effective manner. In this regard, it is desired that the method enable a designer to consider the cost factors involved in manufacturing a high capacity array and identify the most optimal combination of memory die capacity, number of memory dies, assembly, packaging technique, etc. for manufacturing the array.